Caspia Launches New RTL Security Analyzer Enabling Agentic Silicon Security Verification

Caspia Launches New RTL Security Analyzer Enabling Agentic Silicon Security Verification

GAINESVILLE, Fla., Feb. 25: Caspia Technologies announced broad availability of its flagship security verification product CODAx. New and unique capabilities delivered by the product were described, along with its impact on the customer base. The company also provided a preview of its plans to build agentic security verification workflows.

CODAx is Caspia’s security-aware auditing solution that analyzes early (RTL) code of IP/SoC designs to detect coding styles that can introduce security vulnerabilities. Over 150 insecure coding practices are recognized and suggested corrections are also provided.

CODAx security checks are informed by public vulnerability databases including CWE, CVE, and Trust-Hub, which catalog over 1,000 known hardware security weaknesses. Caspia applies GenAI techniques to systematically map these weaknesses to detectable RTL coding patterns.

The latest release of CODAx, V2026.1 provides deeper security checks that span across the design hierarchy, enabling identification of weaknesses that travel up and across design modules. The company reported that comprehensive stress testing was performed on this release with 10,000+ intentionally vulnerable designs.

Caspia also reported that a popular open-source root-of-trust design containing 400+ design files, approximately 3 million gates, and 500,000 lines of RTL code was analyzed by CODAx in about 45 minutes. Multiple security weaknesses were found during this analysis.

Caspia has been working with all the major EDA suppliers to ensure a smooth integration of its tools with existing design flows. The company also reported that major chip and system companies from around the world are successfully deploying CODAx for designs that support applications such as automotive, data center, communication, storage, multimedia, precision analog and embedded computing.

Caspia announced that Stuart Audley has joined the company as VP/GM of product management, with a focus on agentic security workflows. Audley brings decades of experience designing and deploying cryptographic hardware and security IP for top defense primes and leading semiconductor companies. He previously led advanced security platform development for FPGAs and ASICs at The Athena Group, Inc. and Mercury Systems.

“We are expanding our security verification footprint to include both advanced tools and enablement of agentic workflows,” said Rick Hegberg, CEO of Caspia. “I am delighted to add someone with Stuart’s experience and background to the team. This will ensure we can focus on delivering cutting-edge capabilities and AI-driven security automation.”

“Caspia is evolving from a provider of point security verification tools to an agentic platform supplier where AI orchestrates comprehensive hardware security workflows,” said Audley.

He went on to say, “the elements of our plan include unifying all our tools with AI-assisted workflows that span the entire hardware security lifecycle: analyzing RTL, identifying vulnerabilities, and verifying the results.

Traditional design flows remain fully supported, but we are creating a new category for agentic-enabled hardware security verification.”

Caspia will present its latest technology in booth 702 at DVCon on March 2-5, 2026, to be held at the Santa Clara Hyatt Regency in Santa Clara, CA.